SH7619_09 Datasheet, PDF (178/860 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 7 Bus State Controller (BSC)
7.4.4 SDRAM Control Register (SDCR)
SDCR specifies the method to refresh and access SDRAM, and the types of SDRAMs to be
connected.
Initial
Bit
Bit Name Value R/W
31 to 12 
All 0 R
11
RFSH
0
R/W
10
RMODE 0
R/W
9

0
R
8
BACTV 0
R/W
7 to 5 
All 0 R
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Refresh Control
Specifies whether or not the refreshing SDRAM is
performed.
0: Refreshing is not performed
1: Refreshing is performed
Refresh Control
Specifies whether to perform auto-refreshing or self-
refreshing when the RFSH bit is 1. When the RFSH bit is
1 and this bit is 1, self-refreshing starts immediately.
When the RFSH bit is 1 and this bit is 0, auto-refreshing
starts according to the contents that are set in RTCSR,
RTCNT, and RTCOR.
0: Auto-refreshing is performed
1: Self-refreshing is performed
Reserved
This bit is always read as 0. The write value should
always be 0.
Bank Active Mode
Specifies whether to access in auto-precharge mode
(using READA and WRITA commands) or in bank active
mode (using READ and WRIT commands).
0: Auto-precharge mode (using READA and WRITA
commands)
1: Bank active mode (using READ and WRIT commands)
Reserved
These bits are always read as 0. The write value should
always be 0.
Rev. 6.00 Jul. 15, 2009 Page 138 of 816
REJ09B0237-0600