SH7619_09 Datasheet, PDF (203/860 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 7 Bus State Controller (BSC)
Table 7.14 Relationship between Register Settings (BSZ[1:0], A3ROW[1:0], and
A3COL[1:0]) and Address Multiplex Output (3)
Setting
BSZ
[1:0]
A3
ROW
[1:0]
A3
COL
[1:0]
11
(32 bits)
10
(13 bits)
01
(9 bits)
Output Pins of
This LSI
Output Row
Address
Output Column
Address
Pins of SDRAM Function
A17
A26
A17
A16
A25*²
A25*²
A15
A24*²
A24*²
A14 (BA1)
A13 (BA0)
Unused
Specifies bank
A14
A23
A14
A12
Address
A13
A22
A12
A21
A13
L/H*¹
A11
A10/AP
Specifies address/precharge
A11
A20
A11
A9
Address
A10
A19
A10
A8
A9
A18
A9
A7
A8
A17
A8
A6
A7
A16
A7
A5
A6
A15
A6
A4
A5
A14
A5
A3
A4
A13
A4
A2
A3
A12
A3
A1
A2
A11
A2
A0
A1
A10
A1
Unused
A0
A9
A0
Example of memory connection
One 512-Mbit product (4 Mwords x 32 bits x 4 banks, 9-bit column product)
Two 256-Mbit products (4 Mwords x 16 bits x 4 banks, 9-bit column product)
Notes: 1. L/H is a bit used in the command specification; it is fixed low or high according to the
access mode.
2. Bank address specification
Rev. 6.00 Jul. 15, 2009 Page 163 of 816
REJ09B0237-0600