SH7619_09 Datasheet, PDF (839/860 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Item
Page Revision (See Manual for Details)
16.3.4 Receive Data Register 456
(SIRDR)
Added
SIRDR is a 32-bit read-only register that reads receive data
of the SIOF. SIRDR stores data in the receive FIFO and is
initialized to undefined value by the conditions specified in
section 24, List of Registers, or by a receive reset caused
by the RXRST bit in SICTR.
Amended
Initial
Bit
Bit Name Value
R/W
31 to 16 SIRDL
15 to 0
Undefined R
15 to 0
SIRDR
15 to 0
Undefined R
16.3.7 Status Register
(SISTR)
464 Deleted
Bit Description
0
Receive FIFO Overflow
0: No receive FIFO overflow
1: Receive FIFO overflow
A receive FIFO overflow means that writing has occurred
when the receive FIFO is full.
When a receive FIFO overflow occurs, the SIOF
indicates overflow, and receive data is lost.
• This bit is valid when the RXE bit in SICTR is 1.
• When 1 is written to this bit, the contents are
cleared. Writing 0 to this bit is invalid.
• If the issue of interrupts by this bit is enabled, an
SIOF interrupt is issued.
Table 16.7 Audio Mode
482
Specification for Receive Data
Deleted
Note: Left and right same audio mode is not supported in
receive data.
To execute 8-bit monaural transmission or
reception, use the left channel.
Rev. 6.00 Jul. 15, 2009 Page 799 of 816
REJ09B0237-0600