SH7619_09 Datasheet, PDF (421/860 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 15 Serial Communication Interface with FIFO (SCIF)
15.3 Register Description
The SCIF has the following registers. These registers specify the data format and bit rate, and
control the transmitter and receiver sections.
• Receive FIFO data register_0 (SCFRDR_0)
• Transmit FIFO data register_0 (SCFTDR_0)
• Serial mode register_0 (SCSMR_0)
• Serial control register_0 (SCSCR_0)
• Serial status register_0 (SCFSR_0)
• Bit rate register_0 (SCBRR_0)
• FIFO control register_0 (SCFCR_0)
• FIFO data count register_0 (SCFDR_0)
• Serial port register_0 (SCSPTR_0)
• Line status register_0 (SCLSR_0)
• Receive FIFO data register_1 (SCFRDR_1)
• Transmit FIFO data register_1 (SCFTDR_1)
• Serial mode register_1 (SCSMR_1)
• Serial control register_1 (SCSCR_1)
• Serial status register_1 (SCFSR_1)
• Bit rate register_1 (SCBRR_1)
• FIFO control register_1 (SCFCR_1)
• FIFO data count register_1 (SCFDR_1)
• Serial port register_1 (SCSPTR_1)
• Line status register_1 (SCLSR_1)
• Receive FIFO data register_2 (SCFRDR_2)
• Transmit FIFO data register_2 (SCFTDR_2)
• Serial mode register_2 (SCSMR_2)
• Serial control register_2 (SCSCR_2)
• Serial status register_2 (SCFSR_2)
• Bit rate register_2 (SCBRR_2)
• FIFO control register_2 (SCFCR_2)
• FIFO data count register_2 (SCFDR_2)
• Serial port register_2 (SCSPTR_2)
• Line status register_2 (SCLSR_2)
Rev. 6.00 Jul. 15, 2009 Page 381 of 816
REJ09B0237-0600