SH7619_09 Datasheet, PDF (513/860 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 16 Serial I/O with FIFO (SIOF)
16.3.13 Control Data Assign Register (SICDAR)
SICDAR is a 16-bit readable/writable register that specifies the position of the control data in a
frame (slot number). SICDAR can be specified only when the FL bit in SIMDR is specified as
1xxx (x: Don't care.).
Initial
Bit
Bit Name Value
15
CD0E
0
14 to 12 
All 0
11
CD0A3 0
10
CD0A2 0
9
CD0A1 0
8
CD0A0 0
7
CD1E
0
6 to 4 
All 0
R/W Description
R/W Control Channel 0 Data Enable
0: Disables transmission and reception of control
channel 0 data
1: Enables transmission and reception of control channel
0 data
R
Reserved
These bits are always read as 0. The write value should
always be 0.
R/W Control Channel 0 Data Assigns 3 to 0
R/W Specify the position of control channel 0 data in a
R/W ^{receive or transmit frame as B'0000 (0) to B'1110 (14).}
R/W ^{1111: Setting prohibited}
• Transmit data for the control channel 0 data is
specified in the SITD0 bit in SITCR.
• Receive data for the control channel 0 data is stored
in the SIRD0 bit in SIRCR.
R/W Control Channel 1 Data Enable
0: Disables transmission and reception of control
channel 1 data
1: Enables transmission and reception of control channel
1 data
R
Reserved
These bits are always read as 0. The write value should
always be 0.
Rev. 6.00 Jul. 15, 2009 Page 473 of 816
REJ09B0237-0600