SH7619_09 Datasheet, PDF (22/860 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

21.4.3 TDO Output Timing ......................................................................................... 627
21.4.4 H-UDI Reset ..................................................................................................... 628
21.4.5 H-UDI Interrupt ................................................................................................ 628
21.5 Boundary Scan.................................................................................................................. 629
21.5.1 Supported Instructions ...................................................................................... 629
21.5.2 Points for Attention........................................................................................... 630
21.6 Usage Notes ...................................................................................................................... 630
Section 22 Ethernet Physical Layer Transceiver (PHY) ................................... 631
22.1 Features............................................................................................................................. 631
22.2 Pin Configuration.............................................................................................................. 633
22.3 Top Level Functional Architecture................................................................................... 634
22.4 PHY Management Control ............................................................................................... 635
22.4.1 Serial Management Interface (SMI) ................................................................. 635
22.4.2 SMI Register Mapping...................................................................................... 642
22.5 100Base-TX Transmit....................................................................................................... 648
22.6 100Base-TX Receive ........................................................................................................ 651
22.7 10Base-T Transmit ........................................................................................................... 654
22.8 10Base-T Receive............................................................................................................. 656
22.9 MAC Interface .................................................................................................................. 657
22.10 Miscellaneous Functions................................................................................................... 661
22.11 Internal I/O Signals........................................................................................................... 665
22.12 Signals Relevant to PHY-IF ............................................................................................. 667
22.13 Usage Notes ...................................................................................................................... 668
22.14 Guidelines for Layout ....................................................................................................... 678
22.14.1 General Guidelines ........................................................................................... 678
22.14.2 Guidelines for Layout ....................................................................................... 679
Section 23 PHY Interface (PHY-IF) ................................................................. 683
23.1 Features............................................................................................................................. 683
23.2 Register Descriptions........................................................................................................ 685
23.2.1 PHY-IF Control Register (PHYIFCR).............................................................. 685
23.2.2 PHY-IF SMI Register 2 (PHYIFSMIR2) ......................................................... 686
23.2.3 PHY-IF SMI Register 3 (PHYIFSMIR3) ......................................................... 687
23.2.4 PHY-IF Address Register (PHYIFADDRR) .................................................... 687
23.2.5 PHY-IF status Register (PHYIFSR) ................................................................. 688
23.3 PHY-IF Operation ............................................................................................................ 689
23.3.1 The Procedures of Setting Up the On-Chip PHY ............................................. 689
23.3.2 The Procedures of Set Up the External PHY LSI ............................................. 690
Rev. 6.00 Jul. 15, 2009 Page xx of xxxviii