SH7619_09 Datasheet, PDF (716/860 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 22 Ethernet Physical Layer Transceiver (PHY)
• Targets in manufacturing
The table below shows the targets in manufacturing. Each target can be adjusted with the
adjustment registers.
Time division
Target in
Division # _{manufacturing}
Voltage level corresponding
to time division
Target in
Voltage level # _{manufacturing}
Division 1
1 ns
Division 2
2 ns
Division 3
3 ns
Division 4
4 ns
Sublevel 1
Sublevel 2
Sublevel 3
Sublevel 4
250 mV
500 mV
750 mV
1V
Time ranges evenly divided (Tr/4) are
adjusted on DnSL bits, and consequently
the total Tr value is also adjusted.
→"Transition time is controlled on DnSL"
Each sublevel is adjusted on the Vout
value, controlled on DnA bits (evenly
divided by Vout/4).
→"Amplitude is controlled on DnA"
• Adjustment effects
The amplitude and the transition time (the slope) are controlled independently, as shown
above.
The slope is controlled on the DnSL bits and DnCMP bits together. However, since it is
difficult to express the generated analog waveforms quantitatively, the waveforms must be
ensured on the actual boards.
(d) Other Control Methods
The methods, shown below for your reference, may have some bad effects or disadvantages.
Therefore, if the methods will be used, it is necessary to confirm the advantage and disadvantage
sufficiently.
Rev. 6.00 Jul. 15, 2009 Page 676 of 816
REJ09B0237-0600