SH7619_09 Datasheet, PDF (283/860 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 11 Ethernet Controller (EtherC)
11.3.3 EtherC Interrupt Permission Register (ECSIPR)
ECSIPR is a 32-bit readable/writable register that enables or disables the interrupt sources
indicated by ECSR. Each bit can disable or enable interrupts corresponding to the bits in ECSR.
Bit Bit Name
31 to 5 
4
PSRTOIP
3
—
2
LCHNGIP
1
MPDIP
0
ICDIP
Initial
Value
All 0
0
0
0
0
0
R/W Description
R
Reserved
These bits are always read as 0. The write value
should always be 0.
R/W PAUSE Frame Retransfer Retry Over Interrupt Enable
0: Interrupt notification by the PSRTO bit is disabled
1: Interrupt notification by the PSRTO bit is enabled
R
Reserved
This bit is always read as 0. The write value should
always be 0.
R/W LINK Signal Changed Interrupt Enable
0: Interrupt notification by the LCHNG bit is disabled
1: Interrupt notification by the LCHNG bit is enabled
R/W Magic Packet Detection Interrupt Enable
0: Interrupt notification by the MPD bit is disabled
1: Interrupt notification by the MPD bit is enabled
R/W Illegal Carrier Detection Interrupt Enable
0: Interrupt notification by the ICD bit is disabled
1: Interrupt notification by the ICD bit is enabled
Rev. 6.00 Jul. 15, 2009 Page 243 of 816
REJ09B0237-0600