SH7619_09 Datasheet, PDF (557/860 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 17 Host Interface (HIF)
Initial
Bit Bit Name Value R/W Description
1
BYTE1 0
R/W* Internal Register Byte Specification
0
BYTE0 0
R/W*
These bits specify in advance the target word location
before the external device accesses a register among
HIFGSR, HIFSCR, HIFMCR, HIFIICR, HIFEICR, HIFADR,
HIFDATA, and HIFBCR. See also section 17.9, Alignment
Control.
• When HIFSCR.BO = 0
00: Bits 31 to 16 in register
01: Setting prohibited
10: Bits 15 to 0 in register
11: Setting prohibited
• When HIFSCR.BO = 1
00: Bits 15 to 0 in register
01: Setting prohibited
10: Bits 31 to 16 in register
11: Setting prohibited
However, when HIFDATA is selected using bits REG5 to
REG0, each time reading or writing of HIFDATA occurs,
these bits change according to the following rule.
00 → 10 → 00 → 10... repeated
Note: * This bit can be only written to by an external device while the HIFRS pin is held high. It
cannot be written to by the on-chip CPU.
Rev. 6.00 Jul. 15, 2009 Page 517 of 816
REJ09B0237-0600