SH7619_09 Datasheet, PDF (35/860 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Tables
Section 1 Overview
Table 1.1 Features of SH7619 .................................................................................................. 2
Table 1.2 Pin Functions ............................................................................................................ 9
Table 1.3 Pin Features ............................................................................................................ 17
Section 2 CPU
Table 2.1 Initial Values of Registers....................................................................................... 27
Table 2.2 Word Data Sign Extension...................................................................................... 29
Table 2.3 Delayed Branch Instructions................................................................................... 30
Table 2.4 T Bit ........................................................................................................................ 30
Table 2.5 Access to Immediate Data ...................................................................................... 31
Table 2.6 Access to Absolute Address.................................................................................... 31
Table 2.7 Access with Displacement ...................................................................................... 32
Table 2.8 Addressing Modes and Effective Addresses........................................................... 32
Table 2.9 Instruction Formats ................................................................................................. 36
Table 2.10 Instruction Types .................................................................................................... 39
Section 3 Cache
Table 3.1 LRU and Way to be Replaced ................................................................................ 54
Table 3.2 Correspondence between Divided Areas and Cache............................................... 55
Section 5 Exception Handling
Table 5.1 Types of Exceptions and Priority............................................................................ 67
Table 5.2 Timing for Exception Detection and Start of Exception Handling ......................... 68
Table 5.3 Vector Numbers and Vector Table Address Offsets............................................... 69
Table 5.4 Calculating Exception Handling Vector Table Addresses ...................................... 70
Table 5.5 Reset Status............................................................................................................. 71
Table 5.6 Bus Cycles and Address Errors............................................................................... 73
Table 5.7 Interrupt Sources..................................................................................................... 74
Table 5.8 Interrupt Priority ..................................................................................................... 75
Table 5.9 Types of Exceptions Triggered by Instructions ...................................................... 76
Table 5.10 Delay Slot Instructions, Interrupt Disabled Instructions, and Exceptions............... 78
Table 5.11 Stack Status after Exception Handling Ends........................................................... 79
Section 6 Interrupt Controller (INTC)
Table 6.1 Pin Configuration.................................................................................................... 85
Table 6.2 Interrupt Exception Handling Vectors and Priorities............................................ 100
Table 6.3 Interrupt Response Time....................................................................................... 105
Rev. 6.00 Jul. 15, 2009 Page xxxiii of xxxviii