SH7619_09 Datasheet, PDF (20/860 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

17.7.1 HIFIDX Write/HIFGSR Read .......................................................................... 531
17.7.2 Reading/Writing of HIF Registers other than HIFIDX and HIFGSR............... 531
17.7.3 Consecutive Data Writing to HIFRAM by External Device............................. 532
17.7.4 Consecutive Data Reading from HIFRAM to External Device ........................ 532
17.8 External DMAC Interface................................................................................................. 533
17.9 Alignment Control ............................................................................................................ 539
17.10 Interface When External Device Power is Cut Off........................................................... 540
Section 18 Pin Function Controller (PFC) ........................................................ 543
18.1 Register Descriptions........................................................................................................ 553
18.1.1 Port A IO Register H (PAIORH) ...................................................................... 554
18.1.2 Port A Control Register H1 and H2 (PACRH1 and PACRH2) ........................ 554
18.1.3 Port B IO Register L (PBIORL) ....................................................................... 557
18.1.4 Port B Control Register L1 and L2 (PBCRL1 and PBCRL2)........................... 557
18.1.5 Port C IO Register H and L (PCIORH and PCIORL) ...................................... 561
18.1.6 Port C Control Register H2, L1, and L2
(PCCRH2, PCCRL1, and PCCRL2)................................................................. 561
18.1.7 Port D IO Register L (PDIORL)....................................................................... 566
18.1.8 Port D Control Register L2 (PDCRL2)............................................................. 567
18.1.9 Port E IO Register H and L (PEIORH and PEIORL) ....................................... 569
18.1.10 Port E Control Register H1, H2, L1, and L2
(PECRH1, PECRH2, PECRL1, and PECRL2)................................................. 569
18.2 Notes on Usage ................................................................................................................. 577
18.2.1 Restriction in Using .......................................................................................... 577
18.2.2 Details of Restriction ........................................................................................ 577
Section 19 I/O Ports........................................................................................... 579
19.1 Port A................................................................................................................................ 579
19.1.1 Register Description ......................................................................................... 579
19.1.2 Port A Data Register H (PADRH) .................................................................... 579
19.2 Port B................................................................................................................................ 581
19.2.1 Register Description ......................................................................................... 581
19.2.2 Port B Data Register L (PBDRL) ..................................................................... 581
19.3 Port C................................................................................................................................ 583
19.3.1 Register Description ......................................................................................... 584
19.3.2 Port C Data Registers H and L (PCDRH and PCDRL) .................................... 584
19.4 Port D................................................................................................................................ 586
19.4.1 Register Description ......................................................................................... 586
19.4.2 Port D Data Register L (PDDRL)..................................................................... 586
19.5 Port E ................................................................................................................................ 588
Rev. 6.00 Jul. 15, 2009 Page xviii of xxxviii