SH7619_09 Datasheet, PDF (570/860 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 17 Host Interface (HIF)
17.6 Interface (Basic)
Figure 17.3 shows the basic read/write sequence. HIF read is defined by the overlap period of the
HIFRD low-level period and HIFCS low-level period, and HIF write is defined by the overlap
period of the HIFWR low-level period and HIFCS low-level period. The HIFRS signal indicates
whether this is normal access or index/status register access; low level indicates normal access and
high level indicates index/status register access.
HIFCS
HIFRS
HIFRD
HIFWR
HIFD15 to HIFD00
Write cycle
Read cycle
WT_D
RD_D
Figure 17.3 Basic Timing for HIF Interface
Rev. 6.00 Jul. 15, 2009 Page 530 of 816
REJ09B0237-0600