SH7619_09 Datasheet, PDF (400/860 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 13 Direct Memory Access Controller (DMAC)
CKIO
Address
CS
RD
T1 T2 Taw T1 T2
Data
WEn
DACKn
(Active-low)
WAIT
Note: The DACK is asserted for the last transfer unit
of the DMA transfer. When the transfer unit is
divided into several bus cycles and the CS is
negated between bus cycles, the DACK is also
divided.
Figure 13.18 Example of BSC Ordinary Memory Access
(No Wait, Idle Cycle 1, Longword Access to 16-Bit Device)
Rev. 6.00 Jul. 15, 2009 Page 360 of 816
REJ09B0237-0600