SH7619_09 Datasheet, PDF (21/860 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

19.5.1 Register Description ......................................................................................... 589
19.5.2 Port E Data Registers H and L (PEDRH and PEDRL) ..................................... 589
19.6 Usage Notes ...................................................................................................................... 591
Section 20 User Break Controller (UBC) ..........................................................593
20.1 Features............................................................................................................................. 593
20.2 Register Descriptions........................................................................................................ 595
20.2.1 Break Address Register A (BARA) .................................................................. 595
20.2.2 Break Address Mask Register A (BAMRA)..................................................... 596
20.2.3 Break Bus Cycle Register A (BBRA)............................................................... 596
20.2.4 Break Address Register B (BARB) .................................................................. 597
20.2.5 Break Address Mask Register B (BAMRB) ..................................................... 598
20.2.6 Break Data Register B (BDRB) ........................................................................ 598
20.2.7 Break Data Mask Register B (BDMRB)........................................................... 599
20.2.8 Break Bus Cycle Register B (BBRB) ............................................................... 599
20.2.9 Break Control Register (BRCR) ....................................................................... 601
20.2.10 Execution Times Break Register (BETR)......................................................... 604
20.2.11 Branch Source Register (BRSR)....................................................................... 604
20.2.12 Branch Destination Register (BRDR)............................................................... 605
20.3 Operation .......................................................................................................................... 606
20.3.1 Flow of User Break Operation .......................................................................... 606
20.3.2 Break on Instruction Fetch Cycle...................................................................... 607
20.3.3 Break on Data Access Cycle............................................................................. 607
20.3.4 Sequential Break ............................................................................................... 608
20.3.5 Value of Saved Program Counter (PC)............................................................. 608
20.3.6 PC Trace ........................................................................................................... 609
20.3.7 Usage Examples................................................................................................ 610
20.3.8 Notes ................................................................................................................. 614
Section 21 User Debugging Interface (H-UDI) .................................................615
21.1 Features............................................................................................................................. 615
21.2 Input/Output Pins.............................................................................................................. 616
21.3 Register Descriptions........................................................................................................ 617
21.3.1 Bypass Register (SDBPR) ................................................................................ 617
21.3.2 Instruction Register (SDIR) .............................................................................. 617
21.3.3 Boundary Scan Register (SDBSR) ................................................................... 618
21.3.4 ID Register (SDID)........................................................................................... 625
21.4 Operation .......................................................................................................................... 626
21.4.1 TAP Controller ................................................................................................. 626
21.4.2 Reset Configuration .......................................................................................... 627
Rev. 6.00 Jul. 15, 2009 Page xix of xxxviii