SH7619_09 Datasheet, PDF (125/860 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 6 Interrupt Controller (INTC)
6.2 Input/Output Pins
Table 6.1 shows the INTC pin configuration.
Table 6.1 Pin Configuration
Name
Abbr.
Non-maskable interrupt input pin NMI
Interrupt request input pins
IRQ0 to
IRQ7
I/O
Input
Input
Function
Input of non-maskable interrupt request
signal
Input of maskable interrupt request signals
6.3 Register Descriptions
The interrupt controller has the following registers. For details on the addresses of these registers
and the states of these registers in each processing state, see section 24, List of Registers.
• Interrupt control register 0 (ICR0)
• IRQ control register (IRQCR)
• IRQ status register (IRQSR)
• Interrupt priority register A (IPRA)
• Interrupt priority register B (IPRB)
• Interrupt priority register C (IPRC)
• Interrupt priority register D (IPRD)
• Interrupt priority register E (IPRE)
• Interrupt priority register F (IPRF)
• Interrupt priority register G (IPRG)
Rev. 6.00 Jul. 15, 2009 Page 85 of 816
REJ09B0237-0600