SH7619_09 Datasheet, PDF (384/860 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 13 Direct Memory Access Controller (DMAC)
Table 13.4 Selecting External Request Detection with DL, DS Bits
CHCR_0 or CHCR_1
DL
DS
0
0
1
1
0
1
Detection of External Request
Low level detection
Falling edge detection
High level detection
Rising edge detection
When DREQ is accepted, the DREQ pin becomes request accept disabled state. After issuing
acknowledge signal DACK for the accepted DREQ, the DREQ pin again becomes request accept
enabled state.
When DREQ is used by level detection, there are following two cases by the timing to detect the
next DREQ after outputting DACK.
• Overrun 0: Transfer is aborted after the same number of transfer has been performed as
requests.
• Overrun 1: Transfer is aborted after transfers have been performed for (the number of requests
plus 1) times.
The DO bit in CHCR selects this overrun 0 or overrun 1.
Table 13.5 Selecting External Request Detection with DO Bit
CHCR_0 or CHCR_1
DO
0
1
External Request
Overrun 0
Overrun 1
On-Chip Peripheral Module Request Mode: In this mode, a transfer is performed at the transfer
request signal of an on-chip peripheral module. Transfer request signals comprise the transmit data
empty transfer request and receive data full transfer request from the SCIF0, SCIF1, SCIF2, and
SIOF0 set by DMARS0 and DMARS 1.
When this mode is selected, if the DMA transfer is enabled (DE = 1, DME = 1, TE = 0, AE = 0,
NMIF = 0), a transfer is performed upon the input of a transfer request signal.
Rev. 6.00 Jul. 15, 2009 Page 344 of 816
REJ09B0237-0600