SH7619_09 Datasheet, PDF (222/860 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 7 Bus State Controller (BSC)
Figure 7.25 shows the auto-refreshing cycle timing. After starting the auto-refreshing, PALL
command is issued in the Tp cycle to make all the banks to precharged state from active state
when some bank is being precharged. Then the REF command is issued in the Trr cycle after
inserting idle cycles of which number is specified by bits WTRP1 and WTRP0 in CSnWCR. A
new command is not issued for the duration of the number of cycles specified by bits WTRC1
and WTRC0 in CSnWCR after the Trr cycle. Bits WTRC1 and WTRC0 in CSnWCR must be
set so as to satisfy the SDRAM refreshing cycle time (tRC). A Tpw cycle is inserted between
the Tp cycle and Trr cycle when the setting of bits WTRP1 and WTRP0 in CSnWCR is longer
than or equal to two cycles.
CKIO
A25 to A0
A11*
CSn
RAS
CAS
RD/WR
DQMxx
D
BS
Tp
Tpw
Trr
Trc
Trc
Trc
Hi-z
Note: * Address pin to be connected to pin A10 of SDRAM.
Figure 7.25 Auto-Refreshing Timing
Rev. 6.00 Jul. 15, 2009 Page 182 of 816
REJ09B0237-0600