SH7619_09 Datasheet, PDF (358/860 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 12 Ethernet Controller Direct Memory Access Controller (E-DMAC)
(a) Processing transmission without handling of the frame transmission complete (TC)
interrupt
1. Make initial settings for the timer.
2. Prepare multiple transmit descriptors so that multiple frames can be transmitted.
3. After setting the transmit descriptors, start transmission by setting bit 0 (TR) in the E-DMAC
transmit request register (EDTRR).
4. Before setting the next frame for transmission in the transmit descriptor (when a transmission
task arises), check the TACT bit in the corresponding transmit descriptor.
5. If the TACT bit is clear, set the frame for transmission in the corresponding transmit descriptor
and start transmission by setting the TR bit in EDTRR. If the TACT bit is set to 1, set counter i
to 0 (counter i is the variable that indicates the number of repetitions of the timer operation to
measure the specified constant period).
6. Start counting by the timer.
7. When the specified constant period has elapsed, stop the timer counter and check the TACT bit
in the corresponding transmit descriptor.
8. If the TACT bit is clear, set the frame for transmission in the corresponding transmit descriptor
and set the TR bit in EDTRR to start transmission. If the TACT bit is set to 1, increment
counter i.
9. While the TACT bit is found to be 1 in step 8 and the value of counter i is less than n, repeat
steps 6 to 8 until the maximum specified time is reached (the maximum specified time should
be set with reference to the maximum times in consideration of retry processing given in table
12.2, and from this maximum specified time, determine n, the number of repetitions of the
specified constant period; n is determined by the user with reference to table 12.2).
If counter i reaches or exceeds n, the maximum specified time has elapsed and we can judge
that the E-DMAC has stopped due to a transmit underflow. Initialize the EtherC and E-DMAC
modules by setting the software-reset bit SWR in the E-DMAC mode register (EDMR). After
re-making initial settings for the Ethernet module, initialize the transmit/receive descriptors
and transmit/receive buffers.
Rev. 6.00 Jul. 15, 2009 Page 318 of 816
REJ09B0237-0600