SH7619_09 Datasheet, PDF (309/860 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 12 Ethernet Controller Direct Memory Access Controller (E-DMAC)
12.2.1 E-DMAC Mode Register (EDMR)
EDMR is a 32-bit readable/writable register that specifies the operating mode of the E-DMAC.
The settings in this register are normally made in the initialization process following a reset. If the
EtherC and E-DMAC are initialized by means of this register during data transmission, abnormal
data may be sent onto the line. Operating mode settings must not be changed while the transmit
and receive functions are enabled. To change the operating mode, the EtherC and E-DMAC
modules are got into at their initial state by means of the software reset bit (SWR) in this register,
then make new settings. It takes 64 cycles of the internal bus clock Bφ to initialize the EtherC and
E-DMAC. Therefore, registers of the EtherC and E-DMAC should be accessed after 64 cycles of
the internal bus clock Bφ has elapsed.
Initial
Bit
Bit Name value R/W Description
31 to 7 
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
6
DE
0
R/W E-DMAC Data Endian Convert
Selects whether or not the endian format is converted
on data transfer by the E-DMAC. However, the endian
format of the descriptors and E-DMAC register values
are not converted regardless of this bit setting.
0: Endian format not converted (big endian)
1: Endian format converted (little endian)
5
DL1
0
R/W Descriptor Length
4
DL0
0
R/W These bits specify the descriptor length.
00: 16 bytes
01: 32 bytes
10: 64 bytes
11: Reserved (setting prohibited)
3 to 1 
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
Rev. 6.00 Jul. 15, 2009 Page 269 of 816
REJ09B0237-0600