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SH7619_09 Datasheet, PDF (242/860 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series | |||
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Section 8 Clock Pulse Generator (CPG)
A block diagram of the CPG is shown in figure 8.1.
Oscillator unit
CKIO
XTAL
EXTAL
MD2
MD1
MD0
PLL circuit 1
(Ã1, Ã2)
Crystal oscillator
PLL circuit 2
(Ã2, Ã4)
Divider 2
Ã1
Ã1/2
Ã1/4
Ã1/5
Divider 1
Ã1
Ã1/2
Ã1/4
PHY clock
(MÏ)
Internal clock
(IÏ)
Bus clock
(BÏ = CKIO)
Peripheral clock
(PÏ)
Clock frequency
control circuit
CPG control unit
Standby control circuit
FRQCR
MCLKCR STBCR STBCR2 STBCR3 STBCR4
Bus interface
[Legend]
FRQCR: Frequency control register
STBCR: Standby control register
STBCR2: Standby control register 2
STBCR3: Standby control register 3
STBCR4: Standby control register 4
MCLKCR: PHY clock frequency control register
Internal bus
Figure 8.1 Block Diagram of CPG
Rev. 6.00 Jul. 15, 2009 Page 202 of 816
REJ09B0237-0600
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