SH7619_09 Datasheet, PDF (327/860 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 12 Ethernet Controller Direct Memory Access Controller (E-DMAC)
12.2.13 E-DMAC Operation Control Register (EDOCR)
EDOCR is a 32-bit readable/writable register that specifies the control methods used in E-DMAC
operation.
Initial
Bit
Bit Name value R/W Description
31 to 4 
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
3
FEC
0
R/W FIFO Error Control
Specifies E-DMAC operation when transmit FIFO
underflow or receive FIFO overflow occurs.
0: E-DMAC operation continues when underflow or
overflow occurs
1: E-DMAC operation halts when underflow or
overflow occurs
2
AEC
0
R/W Address Error Control
Indicates detection of an illegal memory address in an
attempted E-DMAC transfer.
0: Illegal memory address not detected (normal
operation)
1: E-DMAC stops its operation due to illegal memory
address detection
Note: To resume the operation, set the E-DMAC again
after software reset by means of the SWR bit in
EDMR.
1
EDH
0
R/W E-DMAC Halted
0: The E-DMAC is operating normally
1: The E-DMAC has been halted by NMI pin assertion.
E-DMAC operation is restarted by writing 0
0

0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
Rev. 6.00 Jul. 15, 2009 Page 287 of 816
REJ09B0237-0600