SH7619_09 Datasheet, PDF (635/860 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 20 User Break Controller (UBC)
20.2 Register Descriptions
The user break controller has the following registers. For details on register addresses and access
sizes, refer to section 24, List of Registers.
• Break address register A (BARA)
• Break address mask register A (BAMRA)
• Break bus cycle register A (BBRA)
• Break address register B (BARB)
• Break address mask register B (BAMRB)
• Break bus cycle register B (BBRB)
• Break data register B (BDRB)
• Break data mask register B (BDMRB)
• Break control register (BRCR)
• Execution times break register (BETR)
• Branch source register (BRSR)
• Branch destination register (BRDR)
20.2.1 Break Address Register A (BARA)
BARA is a 32-bit readable/writable register. BARA specifies the address used for a break
condition in channel A.
Bit
31 to 0
Bit Name
BAA31 to
BAA 0
Initial
Value R/W
All 0 R/W
Description
Break Address A
Store the address on the LAB or IAB specifying break
conditions of channel A.
Rev. 6.00 Jul. 15, 2009 Page 595 of 816
REJ09B0237-0600