SH7619_09 Datasheet, PDF (362/860 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 12 Ethernet Controller Direct Memory Access Controller (E-DMAC)
Transmission task
1. Prepare multiple transmit descriptors.
Transmission starts.
After setting the transmit descriptor,
2. _{set the TR bit in EDTRR to 1.}
Next transmission task
No
generated?
Yes
Read the TACT bit of the
corresponding transmit descriptor.
No
3.
TACT = 0?
Yes
4. _{After setting the corresponding transmit}
5. descriptor, set the TR bit in EDTRR to 1.
End
i = 0;
Interrupt handler
Generation of EtherC/E-DMAC
interrupt
Save EESR and clear the bit
by writing 1.
TC interrupt?
No
Yes
Make an OS service call to bring the
transmission task out of the waiting state.
Interrupt other than TC?
No
Yes
Interrupt processing for interrupts
other than TC
End
Call an OS service routine with
4. a timeout function to place the
transmission task in a waiting state.
Has the transmission task
left the waiting state within
*¹
No
he constant specified time?
Yes
5.
Timeout
6.
i++;
i < n? ^*2
Yes
Read the TACT bit of the
corresponding transmit
descriptor.
No
8. _{Issue a software reset to}
initialize the EtherC and
E-DMAC modules.
Make initial settings of the
EtherC and E-DMAC modules.
Initialize the transmit/receive
descriptors and transmit/receive
buffers.
No
7.
TACT = 0?
Yes
Notes: 1. The specified constant period is the timeout period mentioned in section 12.4.1, Usage Notes on SH-Ether EtherC/E-DMAC Status Register
(EESR).
2. Set n with reference to the maximum specified time values in table 12.2.
: Processing added as the countermeasure for the problem
Figure 12.13 Countermeasure for the Case with TC Interrupt-Driven Software: Addition of
Timeout Processing within the Limit Imposed by the Maximum Specified Time
Rev. 6.00 Jul. 15, 2009 Page 322 of 816
REJ09B0237-0600