SH7619_09 Datasheet, PDF (403/860 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 13 Direct Memory Access Controller (DMAC)
CKIO
Bus cycle
DREQ
(Rising edge)
DACK
(High-active)
CPU
1st acceptance
DMAC write or read
2nd acceptance
Non-sensitive period
Non-sensitive period
3rd acceptance is after the
next DACK assertion
Figure 13.20 Example of DREQ Input Detection in Cycle Steal Mode Edge Detection
When DACK is Divided to 2 by Idle Cycles
CKIO
Bus cycle
DREQ
(Overrun 0,
high-level)
DACK
(High-active)
CPU
1st acceptance
Non-sensitive period
DMAC write
2nd acceptance 3rd acceptance possible
Non-sensitive period
CKIO
Bus cycle
DREQ
(Overrun 1,
high-level)
DACK
(High-active)
CPU
DMAC write
1st acceptance
2nd acceptance 3rd acceptance possible
Non-sensitive period Non-sensitive period
Figure 13.21 Example of DREQ Input Detection in Cycle Steal Mode Level Detection
When DACK is Divided to 4 by Idle Cycles
Rev. 6.00 Jul. 15, 2009 Page 363 of 816
REJ09B0237-0600