SH7619_09 Datasheet, PDF (855/860 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Serial I/O with FIFO (SIOF)................... 445
Serial management interface (SMI)........ 635
Shift instructions....................................... 48
Signals relevant to PHY-IF..................... 667
Single address mode ............................... 351
Single read .............................................. 172
Single write............................................. 174
Sleep mode ............................................. 229
SMI register ............................................ 642
Software standby mode........................... 230
SPI mode ................................................ 502
Stack states after exception
handling ends............................................ 79
State transition .......................................... 51
Synchronous mode ................................. 427
System control instructions....................... 49
System registers........................................ 26
T
TAP controller ........................................ 626
The procedures of
set up the external PHY LSI ................... 690
The procedures of
setting up the on-chip PHY..................... 689
Transmit descriptor 0 (TD0) ................... 293
Transmit descriptor 1 (TD1) ................... 295
Transmit descriptor 2 (TD2) ................... 295
Transmitting and receiving serial data
simultaneously (synchronous mode)....... 434
Transmitting serial data
(asynchronous mode) .............................. 420
Transmitting serial data
(synchronous mode)................................ 430
Trap instructions ....................................... 76
Treatment of pins when
PHY power supply is not used................ 668
Types of exception handling and
priority ...................................................... 67
Types of exceptions triggered by
instructions................................................ 76
Types of power-down modes.................. 223
U
U memory ................................................. 65
User break controller (UBC)................... 593
User break interrupt .................................. 99
User debugging interface (H-UDI) ......... 615
W
Wait between access cycles .................... 198
Watchdog timer (WDT) .......................... 215
Write access .............................................. 59
Write-back buffer...................................... 59
Rev. 6.00 Jul. 15, 2009 Page 815 of 816
REJ09B0237-0600