SH7619_09 Datasheet, PDF (672/860 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 22 Ethernet Physical Layer Transceiver (PHY)
Figure 22.1 shows the block diagram around the PHY module.
CPU
This LSI
Internal bus
MII
ETC
(Ether C)
TX-ER
MII_TXD3
MII_TXD2
MII_TXD1
MII_TXD0
TX-EN
TX-CLK
MDC
MDIO
MDI_DIR
MII_RXD3
MII_RXD2
MII_RXD1
MII_RXD0
RX-CLK
CRS
COL
RX-DV
RX-ER
PHY-IF
PHY
CO_TX_ER
CO_MII_TXD3
CO_MII_TXD2
CO_MII_TXD1
CO_MII_TXD0
CO_TX_EN
CO_TX_CLK
CO_MDC
CO_MDI
CO_MDO
CO_MDIO_DIR
CO_MII_RXD3
CO_MII_RXD2
CO_MII_RXD1
CO_MII_RXD0
CO_RX_CLK
CO_CRS
CO_COL
CO_RX_DV
CO_RX_ER
Outside LSI
Tx/Rx
Magnetics
CAT5
LED (_CRS)
LED (_LINK)
LED (_SPEED100)
LED (_FULL-DUPLEX)
Figure 22.1 The Block Diagram around PHY Module
Rev. 6.00 Jul. 15, 2009 Page 632 of 816
REJ09B0237-0600