SH7619_09 Datasheet, PDF (243/860 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 8 Clock Pulse Generator (CPG)
The clock pulse generator blocks function as follows:
PLL Circuit 1: PLL circuit 1 leaves the input clock frequency from the PLL circuit 2 unchanged
or doubles it. The multiplication ratio is set by the frequency control register. The phase of the
rising edge of the internal clock is controlled so that it will match the phase of the rising edge of
the CKIO pin.
PLL Circuit 2: PLL circuit 2 doubles or quadruples the clock frequency input from the crystal
oscillator or the EXTAL pin. The multiplication ratio is fixed for each clock operating mode. The
clock operating mode is set with pins MD0, MD1, or MD2.
Crystal Oscillator: The crystal oscillator is an oscillator circuit when a crystal resonator is
connected to the XTAL and EXTAL pins. The crystal oscillator can be used by setting the clock
operating mode.
Divider 1: Divider 1 generates clocks with the frequencies used by the internal clock, peripheral
clock, and bus clock. The frequency output as the internal clock is always the same as that of the
devider1 output. The frequency output as the bus clock is automatically selected so that it is the
same as the frequency of the CKIO signal according to the multiplication ratio of PLL circuit 1.
The frequencies can be 1, 1/2, or 1/4 times the output frequency of PLL circuit 1, as long as it
stays at or above the frequency of the CKIO pin. The division ratio is set in the frequency control
register.
Divider 2: Divider 2 generates a clock that is supplied to the on-chip PHY. Divider 2 must output
25-MHz frequency for the on-chip PHY that requires 25-MHz clock. The output clock of divider 2
can be 1, 1/2, 1/4, or 1/5 times the output frequency of PLL circuit 1. The division ratio is set in
the PHY clock frequency control register.
Clock Frequency Control Circuit: The clock frequency control circuit controls the clock
frequency using pins MD0, MD1, and MD2, the frequency control register, and PHY clock
frequency control register.
Standby Control Circuit: The standby control circuit controls the state of the on-chip oscillator
circuit and other modules during clock switching and in software standby mode.
Frequency Control Register: The frequency control register has control bits assigned for the
following functions: clock output/non-output from the CKIO pin, the frequency multiplication
ratio of PLL circuit 1, and the frequency division ratio of the peripheral clock.
Standby Control Register: The standby control register has bits for controlling the power-down
modes. For details, see section 10, Power-Down Modes.
Rev. 6.00 Jul. 15, 2009 Page 203 of 816
REJ09B0237-0600