SH7619_09 Datasheet, PDF (529/860 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 16 Serial I/O with FIFO (SIOF)
No.
Flow Chart
1
Start
Set SIMDR, SISCR, SITDAR, SIRDAR,
SICDAR, and SIFCTR
2
Set the SCKE bit to 1 in SICTR
3
Set the FSE bit in SICTR to 1
SIOF Settings
Set operating mode, serial clock,
slot positions for transmit/receive
data, slot position for control data,
and FIFO request threshold value
SIOF Operation
Set operation start for baud rate
generator
Set the start for frame synchronous
signal output
Note: Serial clock will not be output from the
pin until communication is actually
started.
4
Enable transmission and reception Note: Communication is actually started after
Set the TXE, and RXE bit in SICTR to 1
SITDR has been written.
5
TDREQ = 1?
No
Yes
6
Set SITDR register
Set transmit data
7
Transmit SITDR from SIOFTXD
synchronously with SIOFSYNC
Transmission
8
* Please check the TFEMP bit in
No
Transfer complete?
SISTR (the transmit FIFO is
empty?) and build a waiting loop
to check the communication
Yes
finished.
9
Clear the TXE bit in SICTR to 0
Disable transmission
End of transmission
10
To be prepared for the transmission/
Clear the FSE bit in SICTR to 0
reception that is resumed later, set
the FSE bit to '0' to synchronize
the frame in this LSI.
11
Set the MSSEL bit in SISCR to 1
To be prepared for the transmission/
reception that is resumed later,
Set the BPRS to 00000 and the BRDV to 111 in SISCR
initialize inside the baud rate
generator.
Apply a pulse to bits TxRST and RxRST
in the SICTR (input 0→1→0)
Set the SISCR register to set the baud rate
and the master clock source again
12
If communication is not to be
resumed (branching to No), no
Change
No
communication
further setting is needed. To return
to the same communication mode,
mode ?
go back to setting of FSE at step 3
Yes
END
of this flowchart.
13
With FSE = 0, TXE = 0, and RXE = 0 held,
Go on to 'Start' of the corresponding
start setting other bits.
flowchart.
Note: * When interrupts due to transmit data underflow are enabled, after setting the no. 6 transmit data, the TXE bit should be set to 1.
Figure 16.9 (2) Transmission Operation in Master Mode (Example of Half-Duplex
Transmission by the CPU with TDMAE=0)
Rev. 6.00 Jul. 15, 2009 Page 489 of 816
REJ09B0237-0600