SH7619_09 Datasheet, PDF (199/860 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 7 Bus State Controller (BSC)
This LSI
A14
A1
CKE
CKIO
CSn
64-Mbit SDRAM
(1 Mword x 16 bits x 4 banks)
A13
A0
CKE
CLK
CS
RAS
CAS
RD/WR
D15
D0
DQMLU
DQMLL
RAS
CAS
WE
I/O15
I/O0
DQMU
DQML
Figure 7.13 Example of 16-Bit Data-Width SDRAM Connection
Address Multiplexing: An address multiplexing is specified so that SDRAM can be connected
without external multiplexing circuitry according to the setting of bits BSZ1 and BSZ0 in
CSnBCR, AnROW1 and AnROW0 and AnCOL1 AnCOL0 in SDCR. Tables 7.12 to 7.17 show
the relationship between those settings and the bits output on the address pins. Do not specify
those bits in the manner other than this table, otherwise the operation of this LSI is not guaranteed.
A25 to A18 are not multiplexed and the original values of address are always output on these pins.
When the data bus width is 16 bits (BSZ[1:0] = B'10), pin A0 of SDRAM specifies a word
address. Therefore, connect this A0 pin of SDRAM to pin A1 of this LSI; pin A1 pin of SDRAM
to pin A2 of this LSI, and so on. When the data bus width is 32 bits (BSZ[1:0] = B'11), pin A0 of
SDRAM specifies a long word address. Therefore, connect this A0 pin of SDRAM to pin A2 of
this LSI; pin A1 pin of SDRAM to pin A3 of this LSI, and so on.
Rev. 6.00 Jul. 15, 2009 Page 159 of 816
REJ09B0237-0600