SH7619_09 Datasheet, PDF (349/860 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 12 Ethernet Controller Direct Memory Access Controller (E-DMAC)
Bit Bit Name Status
0
CERF CRC error in received frame
"Yes": Setting of this interrupt source bit can fail.
"No": Setting of this interrupt source bit does not fail.
Possibility
of Problem
No
Reflection in
Descriptor
Reflected in
RD0 bit0
(RFS0)
Interrupt
Source
Reception
Take the following countermeasures for bits where the problem can arise.
• Bit 30 (TWB): Write-back complete interrupt source bit in EESR may not be set.
Check the TACT bit in the transmit descriptor. TACT = 0 indicates that the transmission is
complete.
• Bit 26 (TABT): Transmit abort detection interrupt source bit in EESR may not be set.
Since the state of the interrupt source is written back to the relevant descriptor, check the
transmit descriptor (TD0) to confirm the error status.
• Bit 24 (RFCOF): Receive frame counter overflow interrupt source bit in EESR may not be set.
However, even if the software is not notified of the interrupt despite the frame counter having
overflowed, the upper layer (e.g. TCP/IP) can recognize the error because this LSI discards the
frame. After departure from the overflow state, storage in the receive FIFO proceeds normally
from the head of the next frame. Therefore, no problem with the system arises.
• Bit 21 (TC): Frame transmission complete interrupt source bit in EESR may not be set.
For transmission-related processing, either procedure (a) or (b) given below is effective.
(a) Transmission processing without interrupt handling of the frame transmission complete
interrupt
1. Prepare multiple transmit descriptors so that multiple frames can be transmitted.
2. After setting the transmit descriptors, set bit 0 (TR) in the E-DMAC transmit request
register (EDTRR) to start transmission.
3. Before setting the next frame for transmission in the descriptor (when a transmission
task arises), check the TACT bit of the corresponding transmit descriptor.
4. If the TACT bit is clear, set the frame for transmission in the corresponding transmit
descriptor and set the TR bit in EDTRR to start transmission. If the TACT bit is set to
1, do not set the transmit descriptor until the next timing.
(b) For systems where completion of the transmission of each frame must be confirmed (that
is, set frame for transmission → initiate transmission → complete frame transmission →
set the next frame for transmission → …)
1. Check the TACT bit in the last descriptor of the frame for transmission and confirm
that TACT = 0, which means that the transmission was completed.
Rev. 6.00 Jul. 15, 2009 Page 309 of 816
REJ09B0237-0600