SH7619_09 Datasheet, PDF (798/860 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 25 Electrical Characteristics
CKIO
A25 to A0
A11*¹
Td1
Td2
Td3
Td4
Tc1
Tc2
Tc3
Tc4
t_AD1
t_AD1
t_AD1
t_AD1
Column
address
Column
address
Column
address
t_AD1
Read command
Column
address
t_AD1
Tde
t_AD1
CSn
RD/WR
RAS
CAS
DQMxx
t_CSD1
t_RWD
t_RASD
t
CASD
t
DQMD
t_CSD1
t_RWD
t
CASD
t
DQMD
D15 to D0
t_BSD
BS
CKE
t_DACD
DACKn*²
t_RDS2
t_RDH2
t_BSD
(High)
t_RDS2
t_RDH2
t_DACD
Notes: * 1. Address pins connected to A10 in SDRAM
2. DACKn is the waveform when active low is selected.
Figure 25.25 Synchronous DRAM Burst Read Bus Cycle (Single Read × 4)
(Bank Active Mode: READ Command, Same Row Address, CAS Latency = 2,
WTRCD = 0 Cycle)
Rev. 6.00 Jul. 15, 2009 Page 758 of 816
REJ09B0237-0600