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SH7619_09 Datasheet, PDF (802/860 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series
Section 25 Electrical Characteristics
CKIO
A25 to A0
A11*1
Tp
Tpw
Tr
Tc1
Tc2
Tc3
Tc4
tAD1
Row address
tAD1
tAD1
tAD1
tAD1
tAD1
tAD1
tAD1
Column
address
Column
address
Column
address
Column
address
tAD1
tAD1
Write command
CSn
RD/WR
RAS
CAS
DQMxx
tCSD1
tRWD
tRWD
tRASD
tRASD
tRASD
tRWD
tRASD
tCASD
tDQMD
tCSD1
tRWD
tCASD
tDQMD
D15 to D0
BS
CKE
tDACD
tWDD2
t
BSD
tWDH2
(High)
tWDD2
tWDH2
t
BSD
tDACD
DACKn*2
Notes: * 1. Address pins connected to A10 in SDRAM
2. DACKn is the waveform when active low is selected.
Figure 25.29 Synchronous DRAM Burst Write Bus Cycle (Single Write × 4)
(Bank Active Mode: PRE + ACT + WRITE Commands, Different Row Addresses,
WTRCD = 0 Cycle, TRWL = 0 Cycle)
Rev. 6.00 Jul. 15, 2009 Page 762 of 816
REJ09B0237-0600