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SH7619_09 Datasheet, PDF (375/860 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series
Section 13 Direct Memory Access Controller (DMAC)
[Notice]
About the TE bit (Transfer End Flag) of DMA Channel Control Registers (CHCR) in DMAC;
Just when a flag is set to 1, if the flag is read, the read data will be 0, but the internal state will
be the same as reading 1.
In that case, if the flag is written 0, the flag will be cleared as 0, because the internal state is the
same as reading 1.
[Workaround]
In the case of using a flag of DMAC, to protect unintended bit clear to 0, please write it as
following.
(1) In the case of intended bit clear, please write 0 after reading 1 to the flag.
(2) In the other cases, please write 1 to the flag.
If the flag is not used, it is no problem to write 0 to flag (in the case of intended bit clear, write
0 after reading 1 to the flag).
Rev. 6.00 Jul. 15, 2009 Page 335 of 816
REJ09B0237-0600