SH7619_09 Datasheet, PDF (410/860 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 14 Compare Match Timer (CMT)
Initial
Bit
Bit Name value R/W Description
1
CKS1
0
R/W Clock Select 1 and 0
0
CKS0
0
R/W Select the clock to be input to CMCNT from four internal
clocks obtained by dividing the peripheral operating
clock (Pφ). When the STR bit in CMSTR is set to 1,
CMCNT starts counting on the clock selected with bits
CKS1 and CKS0.
00: Pφ/8
01: Pφ/32
10: Pφ/128
11: Pφ/512
Note: * Only 0 can be written, to clear the flag.
14.2.3 Compare Match Counter (CMCNT)
CMCNT is a 16-bit register used as an up-counter. When the counter input clock is selected with
bits CKS1 and CKS0 in CMCSR and the STR bit in CMSTR is set to 1, CMCNT starts counting
using the selected clock.
When the value in CMCNT and the value in compare match constant register (CMCOR) match,
CMCNT is cleared to H'0000 and the CMF flag in CMCSR is set to 1.
CMCNT is initialized to H'0000 by a power-on reset and a transition to standby mode.
14.2.4 Compare Match Constant Register (CMCOR)
CMCOR is a 16-bit register that sets the interval up to a compare match with CMCNT.
CMCOR is initialized to H'FFFF by a power-on reset and is initialized to H'FFFF in standby
mode.
Rev. 6.00 Jul. 15, 2009 Page 370 of 816
REJ09B0237-0600