SH7619_09 Datasheet, PDF (519/860 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 16 Serial I/O with FIFO (SIOF)
Transmit/Receive Timing: The SIOFTxD transmit timing and SIOFRxD receive timing relative
to the SIOFSCK can be set as the sampling timing in the following ways. The transmit/receive
timing is set using the REDG bit in SIMDR.
• Falling-edge sampling
• Rising-edge sampling
Figure 16.4 shows the transmit/receive timing.
(a) Falling-edge sampling
SIOFSCK
(a) Rising-edge sampling
SIOFSCK
SIOFSYNC
SIOFTxD
SIOFRxD
Receive timing
Transmit timing
SIOFSYNC
SIOFTxD
SIOFRxD
Figure 16.4 SIOF Transmit/Receive Timing
Receive timing
Transmit timing
16.4.3 Transfer Data Format
The SIOF performs the following transfer.
• Transmit/receive data: Transfer of 8-bit data/16-bit data/16-bit stereo data
• Control data: Transfer of 16-bit data (uses the specific register as interface)
Transfer Mode: The SIOF supports the following four transfer modes as listed in table 16.4. The
transfer mode can be specified by the TRMD1 and TRMD0 bits in SIMDR.
Table 16.4 Serial Transfer Modes
Transfer Mode
Slave mode 1
Slave mode 2
Master mode 1
Master mode 2
SIOFSYNC
Synchronous pulse
Synchronous pulse
Synchronous pulse
L/R
Bit Delay
SYNCDL bit
No
Control Data
Slot position
Secondary FS
Slot position
Not supported
Rev. 6.00 Jul. 15, 2009 Page 479 of 816
REJ09B0237-0600