SH7619_09 Datasheet, PDF (31/860 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Figure 19.4 Port D ...................................................................................................................... 586
Figure 19.5 Port E....................................................................................................................... 588
Section 20 User Break Controller (UBC)
Figure 20.1 Block Diagram of UBC........................................................................................... 594
Section 21 User Debugging Interface (H-UDI)
Figure 21.1 Block Diagram of H-UDI........................................................................................ 615
Figure 21.2 TAP Controller State Transitions ............................................................................ 626
Figure 21.3 H-UDI Data Transfer Timing.................................................................................. 628
Figure 21.4 H-UDI Reset............................................................................................................ 628
Section 22 Ethernet Physical Layer Transceiver (PHY)
Figure 22.1 The Block Diagram around PHY Module ............................................................... 632
Figure 22.2 Architectural Overview ........................................................................................... 634
Figure 22.3 How to Derive MDIO Signal from Core Signals .................................................... 635
Figure 22.4 MDIO Timing and Frame Structure (READ Cycle) ............................................... 636
Figure 22.5 MDIO Timing and Frame Structure (WRITE Cycle).............................................. 636
Figure 22.6 100Base-TX Data Path ............................................................................................ 648
Figure 22.7 Receive Data Path ................................................................................................... 651
Figure 22.8 Relationship between Received Data and Some MII Signals.................................. 653
Figure 22.9 Manchester Encoded Output ................................................................................... 655
Figure 22.10 Example of Connection with a Pulse Transformer (RJ45) .................................... 679
Section 23 PHY Interface (PHY-IF)
Figure 23.1 Block Diagram of PHY-IF ...................................................................................... 684
Section 25 Electrical Characteristics
Figure 25.1 External Clock Input Timing................................................................................... 736
Figure 25.2 CKIO Clock Output Timing and CK_PHY Clock Input Timing ............................ 736
Figure 25.3 Oscillation Settling Timing after Power-On............................................................ 737
Figure 25.4 Oscillation Settling Timing after Standby Mode (By Reset)................................... 737
Figure 25.5 Oscillation Settling Timing after Standby Mode (By NMI or IRQ)........................ 737
Figure 25.6 PLL Synchronize Settling Timing By Reset or NMI .............................................. 738
Figure 25.7 Reset Input Timing.................................................................................................. 739
Figure 25.8 Interrupt Input Timing............................................................................................. 740
Figure 25.9 Pin Drive Timing in Standby Mode ........................................................................ 740
Figure 25.10 Basic Bus Timing: No Wait Cycle ........................................................................ 743
Figure 25.11 Basic Bus Timing: One Software Wait Cycle ....................................................... 744
Figure 25.12 Basic Bus Timing: One External Wait Cycle ........................................................ 745
Figure 25.13 Basic Bus Timing: One Software Wait Cycle, External Wait Enabled
(WM Bit = 0), No Idle Cycle ................................................................................ 746
Rev. 6.00 Jul. 15, 2009 Page xxix of xxxviii