SH7619_09 Datasheet, PDF (643/860 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 20 User Break Controller (UBC)
Initial
Bit
Bit Name Value R/W Description
6
PCBB 0
R/W PC Break Select B
Selects the break timing of the instruction fetch cycle for
channel B as before or after instruction execution.
0: PC break of channel B is set before instruction
execution
1: PC break of channel B is set after instruction execution
5, 4
—
All 0 R
Reserved
These bits are always read as 0. The write value should
always be 0.
3
SEQ
0
R/W Sequence Condition Select
Selects two conditions of channels A and B as
independent or sequential conditions.
0: Channels A and B are compared under independent
conditions
1: Channels A and B are compared under sequential
conditions (channel A, then channel B)
2, 1
—
All 0 R
Reserved
These bits are always read as 0. The write value should
always be 0.
0
ETBE 0
R/W Number of Execution Times Break Enable
Enables the execution-times break condition only on
channel B. If this bit is 1 (break enable), a user break is
issued when the number of break conditions matches with
the number of execution times that is specified by BETR.
0: The execution-times break condition is disabled on
channel B
1: The execution-times break condition is enabled on
channel B
Rev. 6.00 Jul. 15, 2009 Page 603 of 816
REJ09B0237-0600