SH7619_09 Datasheet, PDF (447/860 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 15 Serial Communication Interface with FIFO (SCIF)
Initial
Bit
Bit Name value R/W Description
3
MCE
0
R/W Modem Control Enable
Enables modem control signals CTS and RTS.
In synchronous mode, clear this bit to 0.
This bit is available only in SCFCR_0 and SCFCR_1. In
SCFCR_2, this bit is reserved. The initial value is 0 and
the write value should always be 0.
0: Modem signal disabled*
1: Modem signal enabled
Note: * The CTS pin state has no effect on transmit
operations regardless of the input value. The
RTS pin state has no effect on receive
operations, either.
2
TFRST
0
R/W Transmit FIFO Data Register Reset
Disables the transmit data in the transmit FIFO data
register and resets the data to the empty state.
0: Reset operation disabled*
1: Reset operation enabled
Note: * Reset operation is executed by a power-on
reset.
1
RFRST
0
R/W Receive FIFO Data Register Reset
Disables the receive data in the receive FIFO data
register and resets the data to the empty state.
0: Reset operation disabled*
1: Reset operation enabled
Note: * Reset operation is executed by a power-on
reset.
0
LOOP
0
R/W Loop-Back Test
Internally connects the transmit output pin (TxD) and
receive input pin (RxD) and enables loop-back testing.
0: Loop back test disabled
1: Loop back test enabled
Rev. 6.00 Jul. 15, 2009 Page 407 of 816
REJ09B0237-0600