SH7619_09 Datasheet, PDF (356/860 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 12 Ethernet Controller Direct Memory Access Controller (E-DMAC)
However, as stated in step 3, the read access to the transmit FIFO by the EtherC module will
have been terminated, and the E-DMAC thus stops operating with the transmit FIFO full.
In short, this problem arises when [initial value of RP – WP value < length of remaining frame
data] at the point of the transmit underflow.
Maximum
Transmit FIFO
RP
transmit FIFO capacity
Data for transmission is written
by the E-DMAC.
Transmit FIFO
WP
Increment
Minimum
WP
transmit FIFO capacity
1. Initial state after software reset
Increment
RP
Data for transmission is read
by EtherC
2. Writing and reading of the data for transmission
Maximum
transmit FIFO capacity
Transmit FIFO
WP
RP
Initial state
RP
Data for transmission is written
by the E-DMAC.
Transmit FIFO
RP
Transmit FIFO
is full
WP
Minimum
transmit FIFO capacity
Data for transmission is read by EtherC
3. Transmit-FIFO underflow has occurred
Reading of data for transmission
by EtherC is terminated.
4. Point where the problem makes the E-DMAC stop
WP: Transmit FIFO write pointer
RP: Transmit FIFO read pointer
Figure 12.11 Operation when E-DMAC Stops and the Transmit FIFO
Rev. 6.00 Jul. 15, 2009 Page 316 of 816
REJ09B0237-0600