SH7619_09 Datasheet, PDF (205/860 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 7 Bus State Controller (BSC)
Setting
Setting
BSZ
[1:0]
A3
ROW
[1:0]
A3
COL
[1:0]
BSZ
[1:0]
A3
ROW
[1:0]
A3
COL
[1:0]
10 (16 00 (11
bits) bits)
00 (8 bits)
10 (16 01 (12
bits) bits)
00 (8 bits)
Output
Pins of Output
This Row
LSI
Address
Output
Column
Address
Pins of
SDRAM
Function
Output
Pins of Output
This Row
LSI
Address
Output
Column
Address
Pins of
SDRAM Function
Example of memory connection
Example of memory connection
One 16-Mbit product (512 kwords x 16 bits x 2 banks, 8-
bit column product)
One 64-Mbit products (1 Mword x 16 bits x 4 banks, 8-bit
column product)
Notes: 1. L/H is a bit used in the command specification; it is fixed low or high according to the
access mode.
2. Bank address specification
Table 7.16 Relationship between Register Settings (BSZ[1:0], A3ROW[1:0], and
A3COL[1:0]) and Address Multiplex Output (5)
Setting
BSZ
[1:0]
A3
ROW
[1:0]
A3
COL
[1:0]
10 (16 01 (12
bits) bits)
01 (9 bits)
Output
Pins of Output
This Row
LSI
Address
Output
Column
Address
Pins of
SDRAM
Function
A17 A26
A17
Unused
A16 A25
A16
A15 A24
A14
A23*²
A13
A22*²
A15
A23*²
A22*²
A13 (BA1) Specifies
A12 (BA0) ^bank
A12 A21
A12
A11
Address
Setting
BSZ
[1:0]
A3
ROW
[1:0]
A3
COL
[1:0]
10 (16 01 (12
bits) bits)
10 (10 bits)
Output
Pins of Output
This Row
LSI Address
Output
Column
Address
Pins of
SDRAM Function
A17 A27
A17
Unused
A16 A26
A16
A15 A25
A15
A14
A24*²
A24*²
A13
A23*²
A23*²
A13 (BA1) Specifies
A12 (BA0) ^bank
A12 A22
A12
A11
Address
Rev. 6.00 Jul. 15, 2009 Page 165 of 816
REJ09B0237-0600