SH7619_09 Datasheet, PDF (725/860 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 23 PHY Interface (PHY-IF)
23.2 Register Descriptions
PHY-IF has below registers. Refer to section 24, List of Registers, about the addresses and the
status under each operating condition.
• PHY-IF control register (PHYIFCR)
• PHY-IF SMI register 2 (PHYIFSMIR2)
• PHY-IF SMI register 3 (PHYIFSMIR3)
• PHY-IF address register (PHYIFADDRR)
• PHY-IF status register (PHYIFSR)
23.2.1 PHY-IF Control Register (PHYIFCR)
PHYIFCR is a 16-bit readable/writeable register, which sets the operation mode of the on-chip
PHY module. The changed bit values except co_resetb are taken by the module reset of the on-
chip PHY with co_resetb.
PHYIFCR is initialized by power-on-reset. It is also initialized as H'C000 in the standby mode.
Bit Bit name
15

14
co_resetb
13
clksel
12 to 3 
Initial
value R/W
1
R
1
R/W
0
R/W
0
R/W
Description
Reserved.
This bit is always read as 1. The write value should
always be 1.
Module reset
Resets the on-chip PHY with software.
0: reset state
1: reset state is released (an initial value)
Clock selection
Selects which to provide to on-chip PHY, the internal
clock or the external clock.
0: Uses the internal clock(mck) (an initial value)
1: Uses the external clock (CK_PHY)
Reserved.
These bits are always read as 0. The write value
should always be 0.
Rev. 6.00 Jul. 15, 2009 Page 685 of 816
REJ09B0237-0600