SH7619_09 Datasheet, PDF (164/860 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 7 Bus State Controller (BSC)
• CS3WCR
Initial
Bit
Bit Name Value R/W
31 to 21 
All 0 R
20
BAS
0
R/W
19 to 11 
All 0 R
10
WR3
1
R/W
9
WR2
0
R/W
8
WR1
1
R/W
7
WR0
0
R/W
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Byte Access Selection for Byte-Selection SRAM
Specifies the WEn (BEn) and RD/WR signal timing when
the byte-selection SRAM interface is used.
0: Asserts the WEn (BEn) signal at the read/write timing
(signal used as strobe) and asserts the RD/WR signal
during the write access cycle (signal used as status)
1: Asserts the WEn (BEn) signal during the read/write
access cycle (used as status) and asserts the RD/WR
signal at the write timing (used as strobe)
Reserved
These bits are always read as 0. The write value should
always be 0.
Number of Access Wait Cycles
Specify the number of wait cycles that are necessary for
read access.
0000: 0 cycle
0001: 1 cycle
0010: 2 cycles
0011: 3 cycles
0100: 4 cycles
0101: 5 cycles
0110: 6 cycles
0111: 8 cycles
1000: 10 cycles
1001: 12 cycles
1010: 14 cycles
1011: 18 cycles
1100: 24 cycles
1101: Reserved (setting prohibited)
1110: Reserved (setting prohibited)
1111: Reserved (setting prohibited)
Rev. 6.00 Jul. 15, 2009 Page 124 of 816
REJ09B0237-0600