SH7619_09 Datasheet, PDF (419/860 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 15 Serial Communication Interface with FIFO (SCIF)
Figure 15.1 shows a block diagram of the SCIF for each channel.
Module data bus
SCFRDR
(16 stage)
RxD
SCRSR
SCFTDR
(16 stage)
SCTSR
SCSMR
SCLSR
SCFDR
SCFCR
SCFSR
SCSCR
SCSPTR
SCBRRn
Baud rate
generator
TxD
SCK
Transmission/
reception
control
Parity generation
Parity check
Clock
External clock
CTS
RTS
[Legend]
SCRSR: Receive shift register
SCFRDR: Receive FIFO data register
SCTSR: Transmit shift register
SCFTDR: Transmit FIFO data register
SCSMR: Serial mode register
SCSCR: Serial control register
SCIF
SCFSR: Serial status register
SCBRR: Bit rate register
SCSPTR:Serial port register
SCFCR: FIFO control register
SCFDR: FIFO data count register
SCLSR: Line status register
Figure 15.1 Block Diagram of SCIF
Internal
data bus
Pφ
Pφ/4
Pφ/16
Pφ/64
TXI
RXI
ERI
BRI
Rev. 6.00 Jul. 15, 2009 Page 379 of 816
REJ09B0237-0600