SH7619_09 Datasheet, PDF (51/860 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 1 Overview
Classifi-
cation Abbr.
I/O Pin Name Description
Bus
control
DQMUL
Output Second Byte Selects bits 23 to 16 of SDRAM data bus.
Select
DQMLU
Output Third Byte
Select
Selects bits 15 to 8 of SDRAM data bus.
DQMLL
CE1A
CE1B
CE2A
CE2B
ICIOWR
ICIORD
WE
IOIS16
Output Least
Significant
Byte Select
Selects bits 7 to 0 of SDRAM data bus.
Output PCMCIA Card Chip enable for PCMCIA allocated to area 5
Select Lower
Side
Output PCMCIA Card Chip enable for PCMCIA allocated to area 6
Select Lower
Side
Output PCMCIA Card Chip enable for PCMCIA allocated to area 5
Select Upper
Side
Output PCMCIA Card Chip enable for PCMCIA allocated to area 6
Select Upper
Side
Output PCMCIA I/O Connects to the PCMCIA I/O write strobe pin.
Write Strobe
Output PCMCIA I/O Connects to the PCMCIA I/O read strobe pin.
Read Strobe
Output PCMCIA
Connects to the PCMCIA memory write strobe.
Memory Write
Strobe
Input
PCMCIA
Dynamic Bus
Sizing
In little endian mode, this signal indicates 16-bit bus width of
PCMCIA. In big endian mode, fix this pin low.
Ethernet CRS
controller _COL
Input Carrier Sense Carrier sense pin
Input Collision
Collision detect pin
MII_TXD3 to Output Transmit Data 4-bit transmit data pins
MII_TXD0
TX_EN
Output Transmit
Enable
Indicates that transmit data is on pins MII_TXD3 to
MII_TXD0.
Rev. 6.00 Jul. 15, 2009 Page 11 of 816
REJ09B0237-0600