SH7619_09 Datasheet, PDF (352/860 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 12 Ethernet Controller Direct Memory Access Controller (E-DMAC)
Transmission task
Interrupt handler
1. Prepare multiple transmit descriptors.
2. Prepare the condition flag and turn it off.
Transmission starts
3.
After setting the transmit
descriptor, set the TR bit in EDTRR to 1.
Next transmission task
No
generated?
Yes
End
Read the TACT bit of the
corresponding transmit descriptor.
No
4.
TACT = 0?
Yes
5.
Turn the condition flag on.
5. After setting the corresponding transmit
7. ^{descriptor, set the TR bit in EDTRR to 1.}
Make an OS service call to place
the transmission task in a waiting state.
Generation of EtherC/E-DMAC
interrupt
Save EESR and clear the bit
by writing a 1.
No
TC interrupt?
Yes
Make an OS service call to bring the
transmission task out of the waiting state.
No
Interrupt other than TC?
Yes
Interrupt processing for interrupts
other than TC
No
Is the condition flag on?
Yes
Read the TACT bit of the corresponding
transmit descriptor.
No
TACT = 0?
6.
Has the transmission task
been brought out of the waiting state
by the interrupt handler?
No
Yes
Make an OS service call to bring the
transmission task out of the waiting state.
Yes
Turn off the condition flag.
TC: EESR frame transmission complete
: Processing added as the countermeasure for the problem
End
Figure 12.9 Countermeasure by Monitoring the Transmit Descriptor in Processing of
Interrupts Other than the Frame Transmit Complete (TC) Interrupt
Rev. 6.00 Jul. 15, 2009 Page 312 of 816
REJ09B0237-0600