SH7619_09 Datasheet, PDF (231/860 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 7 Bus State Controller (BSC)
7.5.7 PCMCIA Interface
With this LSI, if address map 2 is selected using the MAP bit in CMNCR, the PCMCIA interface
can be specified in areas 5 and 6. Areas 5 and 6 in the physical space can be used for the IC
memory card and I/O card interface defined in the JEIDA specifications version 4.2 (PCMCIA2.1
Rev. 2.1) by specifying bits TYPE3 to TYPE0 in CSnBCR (n = 5B and 6B) to B'0101. In addition,
bits SA1 and SA0 in CSnWCR (n = 5B and 6B) assign the upper or lower 32 Mbytes of each area
to an IC memory card or I/O card interface. For example, if bits SA1 and SA0 in CS5BWCR are
set to 1 and cleared to 0, respectively, the upper 32 Mbytes and the lower 32 Mbytes of area 5B
are used as an IC memory card interface and I/O card interface, respectively.
When the PCMCIA interface is used, the bus size must be specified as 8 bits or 16 bits using bits
BSZ1 and BSZ0 in CS5BBCR or CS6BBCR.
Figure 7.33 shows an example of a connection between this LSI and the PCMCIA card. To enable
insertion and removal of the PCMCIA card with the system power turned on, tri-state buffers must
be connected between the LSI and the PCMCIA card.
In the JEIDA and PCMCIA standards, operation in big endian mode is not clearly defined.
Consequently, the provided PCMCIA interface in big endian mode is available only for this LSI.
Rev. 6.00 Jul. 15, 2009 Page 191 of 816
REJ09B0237-0600