SH7619_09 Datasheet, PDF (304/860 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 11 Ethernet Controller (EtherC)
11.6 Usage Notes
• Conditions for Setting LCHNG Bit
Even if the level of the signal input to the LNKSTA pin is not changed, the LCHNG bit in
ECSR may be set. It may happen when the pin function is changed from port to LNKSTA by
PCCRH2 of the PFC or when a software reset caused by the SWR bit in EDMR is cleared
while the LNKSTA pin is being driven high.
This is because the LNKSTA signal is internally fixed low when the pin functions as a port or
during the software reset state regardless of the external pin level.
Clear the LCHNG bit before setting the LCHNGIP bit in ECSIPR not to request a LINK signal
changed interrupt accidentally.
• Flow Control Defect 1
Once a PAUSE frame is received while the receiving flow control is enabled in full-duplex
mode (the RXF bit in ECMR = 1), each time when the local station receives a normal unicast
frame (non-PAUSE frame without a CRC error), the TIME parameter specified by the PAUSE
frame that has been previously received is incorrectly applied. As a result, unnecessary waiting
time is generated to slow down the transmission throughput. The TIME parameter value is
maintained until another PAUSE frame is received.
This defect can be prevented if the destination station supports the function to transmit the 0
time PAUSE frame as the same as this LSI does. Enable the use of 0 time PAUSE frame in
this LSI (the ZPF bit in ECMR = 1) before the 0 time PAUSE frame is received from the
destination station. This clears the TIME parameter incorrectly maintained in the EtherC and
prevents the unnecessary waiting time for transmission to be generated.
Note: This defect may be generated only in the R4S76190. In the R4S76191, the defect has been
corrected.
Rev. 6.00 Jul. 15, 2009 Page 264 of 816
REJ09B0237-0600