SH7619_09 Datasheet, PDF (120/860 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 5 Exception Handling
Types
Illegal slot instruction
General illegal instruction
Stack State
SP →
Address of
delayed branch instruction
SR
32 bits
32 bits
SP →
Address of
general illegal instruction
SR
32 bits
32 bits
Rev. 6.00 Jul. 15, 2009 Page 80 of 816
REJ09B0237-0600