SH7619_09 Datasheet, PDF (395/860 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 13 Direct Memory Access Controller (DMAC)
Relationship between Request Modes and Bus Modes by DMA Transfer Category: Table
13.8 shows the relationship between request modes and bus modes by DMA transfer category.
Table 13.8 Relationship between Request Modes and Bus Modes by DMA Transfer
Category
Address
Mode Transfer Category
Request Bus Transfer
Usable
Mode Mode Size (Bits) Channels
Dual
External device with DACK and external External B/C
memory
8/16/32/128 0,1
External device with DACK and memory- External B/C
mapped external device
External memory and external memory All*¹
B/C
External memory and memory-mapped All*¹
B/C
external device
Memory-mapped external device and All*¹
B/C
memory-mapped external device
External memory and on-chip peripheral All*²
C
module
Memory-mapped external device and All*²
C
on-chip peripheral module
On-chip peripheral module and on-chip All*²
C
peripheral module
8/16/32/128 0, 1
8/16/32/128 0 to 5*⁴
8/16/32/128 0 to 5*⁴
8/16/32/128 0 to 5*⁴
8/16/32/128*³ 0 to 5*⁴
8/16/32/128*³ 0 to 5*⁴
8/16/32/128*³ 0 to 5*⁴
Single External device with DACK and external External B/C 8/16/32
0, 1
memory
External device with DACK and memory- External B/C 8/16/32
0, 1
mapped external device
B: Burst mode, C: Cycle steal mode
Notes: 1. External requests and auto requests are all available.
2. External requests, auto requests, and on-chip peripheral module requests are all
available. However, for on-chip peripheral module requests, the request source register
must be designated as the transfer source or the transfer destination.
3. Access size permitted for the on-chip peripheral module register functioning as the
transfer source or transfer destination.
4. If the transfer request is an external request, channels 0 and 1 are only available.
Rev. 6.00 Jul. 15, 2009 Page 355 of 816
REJ09B0237-0600