SH7619_09 Datasheet, PDF (639/860 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 20 User Break Controller (UBC)
20.2.7 Break Data Mask Register B (BDMRB)
BDMRB is a 32-bit readable/writable register. BDMRB specifies bits masked in the break data
specified by BDRB.
Initial
Bit
Bit Name Value R/W Description
31 to 0 BDMB31 to All 0
BDMB 0
R/W Break Data Mask B
Specify bits masked in the break data of channel B
specified by BDRB (BDB31 to BDB0).
0: Break data BDBn of channel B is included in the
break condition
1: Break data BDBn of channel B is masked and is not
included in the break condition
Note: n = 31 to 0
Notes: 1. Specify an operated size when including the value of the data bus in the break
condition.
2. When the byte size is selected as a break condition, the same data must be set in bits
15 to 8 and 7 to 0 in BDRB as the break mask data.
20.2.8 Break Bus Cycle Register B (BBRB)
Break bus cycle register B (BBRB) is a 16-bit readable/writable register, which specifies (1) L bus
cycle or I bus cycle, (2) instruction fetch or data access, (3) read or write, and (4) operand size in
the break conditions of channel B.
Bit
15 to 8
Initial
Bit Name Value
—
All 0
R/W
R
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Rev. 6.00 Jul. 15, 2009 Page 599 of 816
REJ09B0237-0600